The increasing demand of integrating electronic devices onto automotive, industrial, and consumer platforms requires more sophisticated power conversion and distribution designs. Often these electronic devices include embedded processors, memories, and other electronic components that are operated from one battery source. DC-to-DC voltage converters are used to supply different voltages to the different electronic components.
Switching DC-to-DC voltage converters are popular because of their high efficiency over a wide voltage input range. In contemporary low-power switching DC-to-DC converters, voltage regulation is achieved by pulse-width modulation (PWM). In pulse-width modulation, a control circuit produces a rectangular pulse wave that drives an internal transistor (or transistors in a synchronous device), rapidly switching the transistor(s) at a set frequency, typically in the range of a few megahertz. The output voltage of such a DC-to-DC voltage converter is proportional to the duty cycle of the drive pulse. A voltage-feedback or current-feedback control loop allows a PWM controller output to regulate the output voltage in response to load changes. The technique generally works well, but at low loads the efficiency falls off rapidly, which can shorten battery life in portable products, particularly those that spend a lot of time in a “standby” mode.
One technique for improving the efficiency of a DC-to-DC converter at low loads is to introduce a pulse-frequency modulation (PFM) mode at low loads. PFM control is similar to PWM control in that it employs a rectangular pulse train to determine the output voltage of the regulator. However, instead of altering the duty cycle of the pulse train of a fixed frequency to set the output voltage, PFM alters the frequency of a pulse train having a fixed duty cycle.
FIG. 1 is a schematic circuit diagram representing an illustrative DC-to-DC voltage converter 100. The type of DC-to-DC voltage converter 100 depicted in FIG. 1 is sometimes referred to as a buck converter. The DC-to-DC voltage converter 100 includes a power stage 110 that includes a high-side transistor Q1 and a low-side transistor Q2 that serve as switches. In the example of FIG. 1, transistor Q1 is a p-channel transistor and transistor Q2 is an n-channel transistor. The source of transistor Q1 is coupled to a voltage input 102 that is couplable to a power supply. During operation of the DC-to-DC voltage converter 100, the voltage input 102 operates at an input voltage Vin, which is a DC voltage that is to be converted to another DC voltage by the DC-to-DC voltage converter 100. The drain of transistor Q1 is coupled to a switch node N1. The drain of transistor Q2 is coupled to the switch node N1 and the source of transistor Q2 is coupled to a ground node. The ground node may operate at a potential of ground or a potential that is different than or lower than the input voltage Vin. In the illustrative embodiment shown in FIG. 1, the high-side transistor Q1 is a PMOS (p-channel metal-oxide-semiconductor field-effect) transistor and the low-side transistor Q2 is an NMOS (n-channel metal-oxide-semiconductor field-effect) transistor, which constitutes a typical power stage for a DC-to-DC voltage converter.
The DC-to-DC voltage converter 100 further includes an output stage 120 that includes an inductor 112, an output capacitor 114, and an output node 116 that is couplable to a load. A first terminal of inductor 112 is coupled to the switch node N1. The second terminal of the inductor 112 is coupled to the output capacitor 114. The output 116, or output node, of the DC-to-DC voltage converter 100 operates at an output voltage Vout and is coupled to the junction of the inductor 112 and the output capacitor 114. The output voltage Vout is the DC voltage generated by the DC-to-DC voltage converter 100.
The gates of transistors Q1 and Q2 are coupled to a control circuit 130 that generates gate voltages to turn the transistors Q1 and Q2 off and on. Accordingly, the control circuit 130 serves as a switch controller to control the switching function of transistors Q1 and Q2. The DC-to-DC voltage converter 100 receives the input voltage Vin at the input 102. At times when the control circuit 130 is causing the transistors Q1 and Q2 to switch, the control circuit turns transistors Q1 and Q2 on and off such that one transistor is on while the other transistor is off. The on and off periods control the current IL flowing through the inductor 112. The current IL generates a voltage across the output capacitor 114, which is the output voltage VOUT of the DC-to-DC voltage converter 100. As mentioned previously, the DC-to-DC converter 100 shown in FIG. 1 is merely illustrative. The illustrative converter 100 of FIG. 1 employs a synchronous power stage 110 with two synchronous transistors Q1 and Q2. Alternative embodiments can employ a single power stage transistor that drives the output stage 120.
In the pulse-frequency modulation (PFM) operating mode, the switching activity of the transistors Q1 and Q2 is reduced. FIG. 2 is a timing diagram showing the relationship of gate driver signals 200 provided to transistor Q1 , the inductor current IL 210 and the output voltage Vout 220. Note that the gate driver signal provided to transistor Q2 is not shown in FIG. 2, but when transistors Q1 and Q2 are in a switching mode, the gate driver signals for transistors Q1 and Q2 are complementary, such that transistor Q2 is off when transistor Q1 is on and vice versa. As can be seen in FIG. 2, a low value of the rectangular pulse 200 provided to the gate of PMOS transistor Q1 causes the transistor Q1 to turn on, which in turn causes the inductor current IL 210 to rise until the gate driver signal 200 goes high, thus turning transistor Q1 200 off. When the transistor Q1 switches off, the inductor current IL 210 drops until the transistor Q1 200 switches back on again, and so forth. The control circuit 130 of FIG. 1 monitors the output voltage Vout. When the output voltage Vout 220 surpasses an upper voltage threshold Vth2, the control circuit 130 causes the transistor Q1 to stop switching, that is, the control circuit 130 turns off transistor Q1 by providing a high gate driver signal to the gate of transistor Q1. Thus, the output capacitor 114 of the voltage converter 100 is charged with one or several pulses. In the example represented by FIG. 2, the output capacitor 114 is charged with four pulses before the output voltage Vout 220 reaches the upper threshold voltage Vth2. Then the switching activity is stopped by the control circuit 130 and the supply current of the voltage converter 100 is reduced to a minimum. The output capacitor 114 is then discharged by the load current, causing the output voltage Vout 220 to drop. When the output voltage drops below a lower threshold voltage Vth1 the voltage converter 100 is enabled again, i.e., the control circuit 130 causes the transistors Q1 and Q2 to begin switching again, and the output capacitor 114 is charged again.
Depending on the load current, output capacitor 114 and several other parameters, a DC-to-DC voltage converter operating in a pulse-frequency modulation mode such as represented in FIG. 2 generates pulse frequencies much lower than the switching frequency, down to the audio frequency band. As can be seen in FIG. 2, under constant conditions these frequencies are also constant. These low constant frequencies can result in a significant spur energy being generated at the single frequency of PFM operation, which can disturb other sensitive circuits in the system.